Method of forming an embedded memory including forming three silicon or polysilicon layers
US6787419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2003 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Jan 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.