Methods for fabricating transistor gate structures

US6787425B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Antonio Luis Pacheco Rotondaro · Dallas, US
• Trace Hurd · Plano, US
• Stephanie W. Butler · Richardson, US
• Majid Mansoori · Plano, US

Key dates

• Filing date: Jun 16, 2003
• Grant date: Sep 7, 2004
• Expiry date: Jun 16, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0323

Abstract

Methods are presented for fabricating MOS transistors, in which a sacrificial material such as silicon germanium is formed over a gate contact material prior to gate patterning. The sacrificial material is then removed following sidewall spacer formation to provide a recess at the top of the gate structure. The recess provides space for optional epitaxial silicon formation and suicide formation over the gate contact material without overflowing the tops of the sidewall spacers to minimize shorting between the gate and the source/drains in the finished transistor.