Fabrication method of semiconductor integrated circuit device
US6787446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2002 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Jul 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves, or the silicon carbide film or the organic insulating film exposed to the side walls of the interconnection grooves are side-etched. When a lamination film made of a silicon oxide film, an organic insulating film, a silicon oxide film, an organic insulating film and a silicon carbide film is dry-etched to form interconnection grooves over Cu interconnections, a mixed gas of SF6 and NH3 is used as an etching gas for the silicon carbide film to work side walls of the interconnection grooves perpendicularly and further suppress defects that a deposit or a reactant adheres to the surface of the Cu interconnections exposed to the bottom of the interconnection grooves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.