ESD parasitic bipolar transistors with high resistivity regions in the collector
US6787880B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2003 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | May 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/813
Abstract
A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.