Delay line circuit providing clock pulse width restoration in delay lock loops
US6788119B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2003 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Mar 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Delay lock loops (DLLs) that include delay line circuits with an optional clock pulse width restoration feature, and programmable delay circuits that enable the DLLs. A DLL can include optional inversions before and after at least one of the delay lines included in the DLL. Because two inversions are provided, the overall logic of the delay line is preserved. A DLL typically includes several different delay lines. Therefore, by selectively inverting the clock signal between the delay lines, the effect of each delay line on the clock pulse width can be balanced to provide an output clock signal having a pulse width closer to that of the input clock than would be achievable without the use of such selective inversion. In embodiments where the DLL forms a portion of a programmable logic device (PLD), the optional inversions can be controlled, for example, by configuration memory cells of the PLD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.