Adaptive variable frequency clock system for high performance low power microprocessors
US6788156B2 · kind B2 · utility
44Cited by
26References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 6, 2003 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Jun 6, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.