Method and apparatus for Viterbi detector state metric re-normalization
US6788482B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Jul 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6583
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for Viterbi detector state metric re-normalization. The method includes fabricating a Viterbi detector (138) having a predetermined number of states, wherein the Viterbi detector (138) stores a state metric value and a branch metric value for each state, and wherein the Viterbi detector (138) implements a trellis diagram. The method includes constructing a Viterbi detector (138) which can support a state metric value having g+h′ number of bits. The number of bits needed to represent the branch metric value is represented by (g) and the additional number of bits needed to represent the state metric value is represented by (h′). The additional number of bits (h′) is less than the additional number of bits (h) determined using the following inequality: 2h−1−h≧K−1, wherein K represent the constraint length of the trellis diagram.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.