Failed cell address programming circuit and method for programming failed cell address
US6788596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2003 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Feb 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and a failed cell address programming circuit usable therein. The semiconductor memory device as packaged includes a memory cell array having a plurality of memory cells accessed by an internal address, a plurality of redundant memory cells accessed by a failed cell address of a failed memory cell for repairing a failed memory cell, a comparator for comparing data output from the memory cells during testing the semiconductor memory device as packaged and generating a comparative correspondence signal, a mode setting register for storing an externally applied failed cell address programming control signal in response to a mode control signal, an address generating circuit for generating the internal address by buffering and latching an externally applied address, a failed cell address programming circuit for latching the internal address output from the address generating circuit in response to the failed cell address programming control signal when the comparative accordance signal indicates that a failed memory cell is detected and programming the failed cell address which is an address for accessing the failed memory cell; and a failed cell address d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.