Integrated circuit having arbitrated switching between busses
US6789150B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2000 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Aug 2, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (1) includes a processing device (2), a program interface (4, 5) coupled to the processing device (2), a data interface (6, 7) coupled to the processing device. The program interface (4, 5) includes a first address bus (4) and a first data bus (5) and the data interface (6, 7) includes a second address bus (6) and a second data bus (7). The integrated circuit also includes address and data bus switching devices (18) and a control device (16). The address bus switching device (18) is coupled to the first and second address buses (4, 6) and adapted to be coupled to an external address bus (11) and the data bus switching device (18) is adapted to be coupled to an external data bus (12) and is coupled to the first and second data buses (5, 7). The control device (16) is coupled to the processing device (2), the address bus switching device (18) and the data bus switching device (18). The control device (16) controls the address and data bus switching devices (18) to couple the first address bus (4) and the first data bus (5) to the external address and data buses (11, 12) or to couple the second address bus (6) and the second data bus (7) to the external address a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.