Apparatus and method for activation of a digital signal processor in an idle mode for interprocessor transfer of signal groups in a digital signal processing unit
US6789183B1 · kind B1 · utility
30Cited by
11References
12Claims
0Family size
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Key dates
| Filing date | Sep 27, 2000 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Sep 12, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a digital processing unit having a plurality of digital signal processors, a first digital signal processor can request a direct transfer of a signal group stored in the memory unit of a second digital signal processor. In order to insure that the second digital signal is active, a control signal is generated by the direct memory access controller of the first digital signal processor. The control signal is applied the directly to the memory access controller of the second digital signal processor. When the second digital signal processor is in an IDLE mode, the control signal activates the second digital signal processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.