Data processing system having memory including mode register
US6789210B2 · kind B2 · utility
8Cited by
23References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2003 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Jan 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.