Method for producing an integrated semiconductor memory configuration

US6790726B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Marcus Kastner · Ottobrunn, DE
• Thomas Mikolajick · Birkenfeld, DE

Key dates

• Filing date: Jun 30, 2003
• Grant date: Sep 14, 2004
• Expiry date: Jun 30, 2023

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/928

Abstract

A method for producing an integrated semiconductor memory configuration includes forming two capacitor modules for each selection transistor from the front and rear side of the substrate wafer respectively. Thus, a higher packing density of memory cells is engendered by the utilization of the rear side of the wafer. A twofold memory read signal can be used for the same cell surface area. Conditions in addition to “0” or “1” can also be saved for each selection transistor in a ferroelectric memory configuration, if the two capacitor modules have a different structure in terms of layer thickness, surface area, or material.