Thinning techniques for wafer-to-wafer vertical stacks
US6790748B2 · kind B2 · utility
222Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2002 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Feb 28, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for thinning wafer-to-wafer vertical stacks in the fabrication of stacked microelectronic devices. The methods include physically removing unsupported portions of a wafer to be thinned in the vertical stack. The removal of the unsupported portions substantially eliminates potential cracking and chipping of the wafer, which can occur during the thinning process when the unsupported portions exist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.