R. Scott List
40Patents
18h-index
26Co-inventors
77Inventor score
Filing activity: Dec 17, 1997 → Apr 27, 2007
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7157787B2 | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices | Electricity | 765 | Expired |
| US6762076B2 | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices | Electricity | 521 | Expired |
| US6661085B2 | Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack | Electricity | 492 | Expired |
| US6887769B2 | Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same | Electricity | 455 | Expired |
| US7037804B2 | Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration | Electricity | 231 | Expired |
| US6908565B2 | Etch thinning techniques for wafer-to-wafer vertical stacks | Electricity | 228 | Expired |
| US6975016B2 | Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof | Electricity | 225 | Expired |
| US7056807B2 | Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack | Electricity | 222 | Expired |
| US6790748B2 | Thinning techniques for wafer-to-wafer vertical stacks | Emerging Cross-Sectional Technologies | 222 | Expired |
| US7615462B2 | Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack | Electricity | 151 | Active |
| US6059553A | Integrated circuit dielectrics | Emerging Cross-Sectional Technologies | 83 | Expired |
| US7056813B2 | Methods of forming backside connections on a wafer stack | Electricity | 62 | Expired |
| US6897125B2 | Methods of forming backside connections on a wafer stack | Electricity | 59 | Expired |
| US6977435B2 | Thick metal layer integrated process flow to improve power delivery and mechanical buffering | Electricity | 55 | Expired |
| US6645832B2 | Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack | Electricity | 46 | Expired |
| US7148565B2 | Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack | Electricity | 39 | Expired |
| US7129172B2 | Bonded wafer processing method | Emerging Cross-Sectional Technologies | 31 | Expired |
| US7355277B2 | Apparatus and method integrating an electro-osmotic pump and microchannel assembly into a die package | Electricity | 23 | Expired |
| US6870270B2 | Method and structure for interfacing electronic devices | Electricity | 15 | Expired |
| US7696015B2 | Method of forming a stack of heat generating integrated circuit chips with intervening cooling integrated circuit chips | Electricity | 13 | Active |
| US6981849B2 | Electro-osmotic pumps and micro-channels | Electricity | 12 | Expired |
| US7227257B2 | Cooling micro-channels | Electricity | 10 | Expired |
| US6664168B1 | Method of making an on-die decoupling capacitor for a semiconductor device | Electricity | 9 | Expired |
| US7034394B2 | Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same | Electricity | 7 | Expired |
| US6833321B2 | Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability | Electricity | 7 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.