Thin film transistor and multilayer film structure and manufacturing method of same
US6791144B1 · kind B1 · utility
17Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2000 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Jun 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0241
Abstract
The present invention is directed to a thin film transistor (and related multilayer structures) that includes: source and drain electrodes 14 and 15 disposed at a specified interval above an insulating substrate 11 and formed by printing-and-plating; an a-Si-film 16 disposed for the source and drain electrodes 14 and 15; a gate insulating film 17 laminated on the a-Si film 16; and a gate electrode 18 laminated on the gate insulating film 17 and formed by printing-and-plating. The a-Si film 16 and the gate insulating film 17 have an offset region 20 that uniformly extends beyond the dimensions of the gate electrode 18.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.