Source synchronous interface using variable digital data delay lines
US6791360B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2002 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Sep 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A source synchronous interface determines an amount of delay for an incoming data signal and a phase offset for a latch device that latches the incoming data signal. A delay locked loop may be a dual loop delay locked loop, in which case, the loops may use a low jitter, local clock signal and an input clock signal that was transmitted with the data signal. The low jitter, local clock signal may provide a stable source from which to derive good clock signal edge transitions. The input clock signal may be used to determine the long term clock signal drift. A finite state machine within the dual loop delay locked loop may provide the necessary information for the amount of delay and the phase offset. The delay of the incoming data signal is produced by a digital delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.