Nonvolatile semiconductor memory device
US6791882B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2002 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Jul 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.