Concurrent logical and physical construction of voltage islands for mixed supply voltage designs

US6792582B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John M. Cohn · South Burlington, US
• Alvar A. Dean · South Burlington, US
• David J. Hathaway · Underhill Center, US
• David E. Lackey · Jericho, US
• Thomas Lepsic · Jeffersonville, US
• Susan K. Lichtensteiger · South Burlington, US
• Scott A. Tetreault · Saint Albans, US
• Sebastian T. Ventrone · South Burlington, US

Key dates

• Filing date: Nov 15, 2000
• Grant date: Sep 14, 2004
• Expiry date: Nov 25, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/30
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into “bins”, which are areas of the design. In this way, a semiconductor chip design may be “sliced” into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.