Method of manufacturing a semiconductor device including alignment mark
US6794263B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2003 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Feb 19, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.