Method for and structure formed from fabricating a relatively deep isolation structure
US6794269B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Dec 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76202
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.