Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials

US6794705B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Jingyu Lian · Plattekill, US
• Chenting Lin · Poughkeepsie, US
• Nicolas Nagel · Yokohama, JP
• Michael Wise · Washington, US

Key dates

• Filing date: Dec 28, 2000
• Grant date: Sep 21, 2004
• Expiry date: Dec 28, 2020

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/908

Abstract

A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.