High performance PNP bipolar device fully compatible with CMOS process
US6794730B2 · kind B2 · utility
7Cited by
8References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2001 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Dec 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.