Three-dimensional stacked semiconductor package with pillars in pillar cavities
US6794741B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Apr 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, the pillars are disposed outside the peripheries of the chips and aligned with one another, and the first pillar extends into a cavity in the second pillar. The conductive bond is within the cavity and contacts and electrically connects the pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.