Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines
US6794756B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2002 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | May 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76837
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps. Vias are then formed through the standard k silicon oxide dielectric layer and the silicon oxynitride caps down to the metal lines. Since the vias are not formed through the low k silicon oxide dielectri…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.