Memory integrated circuit
US6795329B2 · kind B2 · utility
3Cited by
2References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 20, 2002 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved memory IC whose memory cells are configured in a chain architecture is disclosed. The first diffusion regions of the cell transistors of the chain are coupled to first capacitor electrodes while the second diffusion regions are coupled to second capacitor electrodes. This ensures that the electric field applied across any of the capacitors of the chain by a plateline pulse is in the same direction. This reduces or avoids asymmetrical hysteresis curves for adjacent memory cells, thereby the improving sensing window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.