Bit line sense amplifier driving control circuits and methods for synchronous drams that selectively supply and suspend supply of operating voltages
US6795372B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2003 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Mar 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bit line sense amplifier driving control circuits and methods for synchronous DRAMs selectively supply and suspend supply of operating voltages for bit line sense amplifiers. More specifically, a synchronous DRAM includes a memory cell array including at least a first column block and a second column block that are divided according to column address, first bit line sense amplifiers that are configured to sense data that is output from the first column block of the memory cell array, and second bit line sense amplifiers that are configured to sense data that is output from the second column block of the memory cell array. A bit line sense amplifier driving control circuit or method is responsive to a row address select signal, to supply an operating voltage to the first and second bit line sense amplifiers, and is responsive to a column select signal that selects a column address in the first column block, to suspend supplying an operating voltage to the second bit line sense amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.