Verifying cumulative ordering of memory instructions
US6795878B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2000 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Jul 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified. Upon identifying the first and second reloads of the first and second cache lines, a determination may be made as to whether the first reload occurred after the second. If the first reload did not occur after the second reload, then a determination may be made as to whether the owner…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.