Inventor · Austin, TX, US

Kenneth L. Wright

122Patents
12h-index
123Co-inventors
89Inventor score

Filing activity: Dec 17, 1998 → Nov 17, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9720704B2 Data driven hardware chips initialization via hardware procedure framework Physics 51 Active
US9720703B2 Data driven hardware chips initialization via hardware procedure framework Physics 50 Active
US7948817B2 Advanced memory device having reduced power and improved performance Emerging Cross-Sectional Technologies 41 Active
US11132425B1 Systems and methods for location-binding authentication Physics 19 Active
US9997233B1 Memory module with dynamic stripe width Emerging Cross-Sectional Technologies 19 Active
US8697567B2 Implementing decoupling devices inside a TSV DRAM stack Electricity 16 Active
US7194587B2 Localized cache block flush instruction Physics 16 Expired
US6785773B2 Verification of global coherence in a multi-node NUMA system Physics 14 Expired
US9697884B2 Variable width memory module supporting enhanced error detection and correction Physics 14 Active
US7770067B2 Method for cache correction using functional tests translated to fuse repair Physics 13 Active
US8862953B2 Memory testing with selective use of an error correction code decoder Physics 12 Active
US7979387B2 Personal information system Electricity 12 Active
US9858208B2 System for securing contents of removable memory Physics 10 Active
US8099570B2 Methods, systems, and computer program products for dynamic selective memory mirroring Physics 9 Active
US8775906B2 Efficient storage of meta-bits within a system memory Physics 8 Active
US9436548B2 ECC bypass using low latency CE correction with retry select signal Physics 8 Active
US8352806B2 System to improve memory failure management and associated methods Electricity 8 Active
US6904490B2 Method and system of managing virtualized physical memory in a multi-processor system Physics 8 Expired
US8869007B2 Three dimensional (3D) memory device sparing Physics 8 Active
US7243194B2 Method to preserve ordering of read and write operations in a DMA system by delaying read access Physics 7 Expired
US8890316B2 Implementing decoupling devices inside a TSV DRAM stack Electricity 7 Active
US8023358B2 System and method for providing a non-power-of-two burst length in a memory system Physics 7 Active
US10409742B2 Interface for memory readout from a memory component in the event of fault Emerging Cross-Sectional Technologies 7 Active
US10235242B2 Fault tolerant memory systems and components with interconnected and redundant data interfaces Electricity 7 Active
US7409504B2 Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response Physics 7 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.