Memory system with burst length shorter than prefetch length
US6795899B2 · kind B2 · utility
201Cited by
9References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2002 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Oct 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, the invention includes a system having a memory controller, a bus, and first and second memory devices. The memory controller requests read and write operations and operates with a burst length. The first and second memory devices are coupled to the memory controller through the bus, the first and second memory devices each having a prefetch length that is greater than the burst length, but performing the requested read and write operations with the burst length. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.