Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design
US6795953B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2002 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Sep 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design is described. Described processing includes retrieving conductivity layers information for an integrated circuit design from a GDSII formatted file; defining a dummy polygons layer and a target layer; restoring interconnect polygons from the conductivity layers information into the dummy polygons layer; copying the interconnect polygons from the dummy polygons layer to the target layer, except for dummy interconnect polygons; and performing defect analysis of the integrated circuit design using the target layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.