Fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant, annealed with a buffered anneal process
US6797525B2 · kind B2 · utility
13Cited by
3References
18Claims
0Family size
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Key dates
| Filing date | May 22, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | May 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an annealed high-K metal oxide transistor gate structure is disclosed. A metal oxide layer is formed over a semiconductor substrate. The metal oxide layer undergoes a buffered annealed process in an oxygen atmosphere to anneal the metal oxide layer at or below the thermodynamic chemical equilibrium of SiO/SiO2 and at or above the thermodynamic chemical equilibrium of the metal oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.