Method of fabricating contact holes on a semiconductor chip
US6797611B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2003 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Aug 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating contact holes on a semiconductor chip with a plurality of gates and a first mask layer includes filling a dielectric layer into the inter-gate space of two gates, polishing the dielectric layer until the surface of the dielectric layer is coplanar with the gates, depositing a second mask layer, etching the second mask layer to form a bit line opening in an array area and simultaneously forming a gate opening and a substrate opening in a periphery area, removing a portion of the dielectric layer through the bit line opening and the substrate opening to form a bit line contact hole and a substrate contact hole, filling a metal layer into the bit line contact hole and the substrate contact hole, and etching the first mask layer through the gate opening to form a gate contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.