DRAM
US6798681B2 · kind B2 · utility
2Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Sep 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.