System and method for effectively implementing a high speed DRAM device
US6798687B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 16, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Mar 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for effectively implementing a high-speed DRAM device may include memory cells that each have a bitline for transferring storage data, a wordline for enabling an accelerated-write operation in the memory cell, and a data storage node with a corresponding cell voltage. An accelerated-write circuit may then directly provide the storage data to an appropriate bitline in a pre-toggled state in response to one or more accelerated-write enable signals. The corresponding cell voltage may therefore begin a state-change transition towards the pre-toggled state immediately after the wordline is activated to successfully reach a full-state level before the wordline is deactivated during a high-speed memory cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.