Branch ordering buffer
US6799268B1 · kind B1 · utility
129Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Mar 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A branch ordering buffer. One disclosed apparatus includes a processor state management circuit to maintain a primary state and a shadow state, each of the primary state and the shadow state including mappings from logical registers to physical registers. The primary state is a speculative state. This disclosed apparatus also includes a branch ordering circuit to prevent the shadow state from advancing beyond a branch instruction until commitment of the branch instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.