Method and system for detecting a hard failure in a memory array
US6799291B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2000 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Dec 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for detecting a failure in a dynamic random access memory (DRAM) array having a plurality of cells organized in a matrix fashion of rows and columns. The method includes reading the content of a first row of cells of the memory array during a first refresh cycle. After obtaining the content from the first row of cells, a first complement of the content is generated. The generated first complement is then written back to the first row of cells during the writeback operation of the first refresh cycle. During the subsequent refresh cycle, the first complement in the first row of cells is read and a second complement of the first complement is generated. Next, the original content in the first row of cells is compared with the second complement. In response to the original content not being equal to the second complement, a control signal is generated to indicate a failure in the memory array. In a related embodiment, the second complement is written back to the first row of cells during the subsequent refresh cycle writeback operation to restore the content in the first row of cells to its original value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.