Timing analysis of latch-controlled digital circuits with detailed clock skew analysis
US6799308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Mar 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.