Method of fabricating a MOS transistor with a drain extension and corresponding transistor
US6800514B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/603
Abstract
A MOS transistor with a drain extension includes an isolation block on the upper surface of a semiconductor substrate. The isolation block has a first sidewall next to the gate of the transistor, and a second sidewall that is substantially parallel to the first sidewall. The isolation block further includes a drain extension zone in the substrate under the isolation block, and a drain region in contact with the drain extension zone. The drain region is in the substrate but is not covered by the isolation block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.