Method of manufacturing split gate flash memory device
US6800525B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2003 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Jul 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
The method of manufacturing a split gate flash memory device includes the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) etching the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) etching the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film remained, and exposing the first conductive film provided in a lower part thereof; and (h) etching the first dielectric film and the first conductive film exposed by the removal of the second dielectric film using the fourth dielectric film as an etch mask, and forming a second gate dielectri…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.