Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors

US6800530B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Byoung Hun Lee · Wappingers Falls, US
• Bachir Dirahoui · Mount Kisco, US
• Effendi Leobandung · Stormville, US
• Tai-chi Su · Woodbury, US

Key dates

• Filing date: Jan 14, 2003
• Grant date: Oct 5, 2004
• Expiry date: Jan 14, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

An integrated circuit employing CMOS technology employs a process integration that combines a source/drain silicide with a replacement gate process using a triple layer hardmask that is consumed during the course of processing in which a first temporary gate sidewall spacer defines an area for the formation of the raised source and drain and a second temporary spacer defines an area for the implant of the source and drain and for the siliciding of the source and drain while the temporary gate is protected from silicidaiton by the hardmask.