Bachir Dirahoui
10Patents
3h-index
23Co-inventors
56Inventor score
Filing activity: May 12, 1999 → Sep 15, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6281583A | Planar integrated circuit interconnect | Emerging Cross-Sectional Technologies | 12 | Expired |
| US6800530B2 | Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors | Electricity | 8 | Expired |
| US6492259B2 | Process for making a planar integrated circuit interconnect | Emerging Cross-Sectional Technologies | 8 | Expired |
| US7790553B2 | Methods for forming high performance gates and structures thereof | Electricity | 3 | Active |
| US8901706B2 | Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches | Electricity | 3 | Active |
| US7358130B2 | Method for monitoring lateral encroachment of spacer process on a CD SEM | Electricity | 0 | Active |
| US10573526B2 | Method of charge controlled patterning during reactive ion etching | Electricity | 0 | Active |
| US7105398B2 | Method for monitoring lateral encroachment of spacer process on a CD SEM | Electricity | 0 | Expired |
| US9496148B1 | Method of charge controlled patterning during reactive ion etching | Electricity | 0 | Active |
| US9087927B2 | Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.