Field programmable gate array core cell with efficient logic packing
US6801052B2 · kind B2 · utility
8Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Oct 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.