Clock synchronized non-volatile memory device
US6801452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Nov 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory apparatus including plural terminals having clock, command and other terminals, plural nonvolatile memory cells, and first and second volatile memories. The clock and command terminals receive respectively a first clock signal and commands including read and program commands. In response to the read command, the apparatus reads data from the memory cells, stores read data to the second volatile memory, transfers the data to the first volatile memory, and outputs the data to outside via the other terminal not the command terminal based on the first clock signal. In response to the program command, the apparatus receives data from outside via the other terminal not the command terminal based on the first clock signal, stores the received data to the first volatile memory, transfers the data to the second volatile memory, and writes the data from the second volatile memory to the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.