Method and apparatus for leakage compensation with full Vcc pre-charge
US6801463B2 · kind B2 · utility
20Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Nov 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A leakage compensation approach enabling full VCC precharge. An array of memory cells is coupled between a pair of bit lines. A precharge circuit precharges the pair of bit lines to substantially a supply voltage level and a leakage compensation circuit supplies a first compensation current to a first one of the bit lines to substantially compensate for leakage current supplied by the first bit line during a memory access operation directed to one of the plurality of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.