Read prediction algorithm to provide low latency reads with SDRAM cache
US6801982B2 · kind B2 · utility
2Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Oct 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method of controlling stores to and reads from a cache, if a read request is in a read queue, then a read is performed. If no read is in the read queue and if a store request is in a store queue and if an early read predict signal is not asserted, then a store is performed. If no read is in the read queue and if a store request is in the store queue and if the early read predict signal is asserted, if a read is detected a read is then performed. Otherwise, if the early read predict is subsequently de-asserted, then a store is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.