Parameterizable and reconfigurable debugger core generators
US6802026B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2001 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Dec 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method for debugging a run-time reconfigurable processing arrangement. The processing arrangement includes a host process that hosts a run-time reconfiguration application program and a programmable logic device (PLD). The run-time reconfiguration program specifies a circuit design with references to core generators in a library, generates configuration data that implements the circuit design on the PLD, and configures the PLD with the configuration data. One of the core generators generates a breakpoint circuit that steps the PLD for a selected number of clock cycles. When the PLD is activated, the breakpoint circuit steps the PLD, and state information of one or more selected elements of the PLD is analyzed after stepping the PLD. Depending on the analysis, the breakpoint core generator is re-parameterized and the PLD reconfigured with a new breakpoint circuit to continue debugging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.