Low-power critical error rate communications controller
US6802033B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1999 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Apr 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0053
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.