Method of fabricating dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation
US6803285B2 · kind B2 · utility
6Cited by
17References
13Claims
0Family size
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Key dates
| Filing date | Dec 4, 2002 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Apr 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
Abstract
A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.