Method to preserve alignment mark optical integrity
US6803291B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2003 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Mar 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for protecting an alignment mark area during a CMP process including forming at least a first material layer over a process surface of a semiconductor wafer including active areas and alignment mark trenches formed in the at least one alignment mark area; forming at least a second material layer over the first material layer including the active areas and the at least one alignment mark area; lithographically patterning and etching the at least a second material layer to form at least a plurality lines of the at least a second material layer adjacent to the alignment mark trenches; and, carrying out a CMP process to remove at least a portion of the at least a second material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.