Nitride spacer formation
US6803321B1 · kind B1 · utility
6Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2002 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Dec 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28247
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure comprises forming a nitride layer on a stack, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer. The forming is by CVD with a gas comprising SixL2x, L is an amino group, and X is 1 or 2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.